3-8译码器fpga程序.docVIP

3-8译码器 library ieee; use ieee.std_logic_1164.all;entity decoder3_8 is port(a,b,c,g1,g2a,g2b: in std_logic; y: out std_logic_vector(7 downto 0)); end decoder3_8; architecture rtl OF decoder3_8 is signal indata: std_logic_vector(2 downto 0); begin indata=cba; process(indata,g1,g2a,g2b) begin if(g1=1 and g2a=0 and g2b=0) then case indata is when 000=y when 001=y when 010=y when 011=y when 100=y when 101=y when 110=y when 111=y when others=y=XXXXXXXX; end case; else y end if; end process; end rtl; 8输入、3输出的优先编码器。 library ieee; use ieee.std_logic_1164.all; entity prior is port( input: in std_logic_vector(7 downto 0); y: out std_logic_vector(2 downto 0)); end prior; architecture be_prior OF prior is begin process(input) begin if(input(0)=0) then y=111; elsif (input(1)=0) then y=110; elsif (input(2)=0) then y=101; elsif (input(3)=0) then y=100; elsif (input(4)=0) then y=011; elsif (input(5)=0) then y=010; elsif (input(6)=0) then y=001; elsif (input(7)=0) then y=000; end if; end process; end be_prior; 半加器实现全加器 library ieee; use ieee.std_logic_1164.all; entity full_adder is port( a,b,cin: in std_logic; co,s : out std_logic); end full_adder; architecture beha of full_adder is component half_adder port( a,b : in std_logic; co,s : out std_logic); end component; signal u0_co,u0_s,u1_co:std_logic; begin u0:half_adder port map(a,b,u0_s,u0_co); u1:half_adder port map(u0_s,cin,s,u1_co); co=u0_co or u1_co; end beha; 具有异步清零端的4位二进制计数器 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt4 is port(clk,clr: in std_logic;