中科院_段成华数字集成系统设计_作业5详解.doc

Assignment 5 An 8-bit Up And Down Synchronous Counter VHDL Module ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --------------------------------------- -----综合时，数据流端加上拉电阻，要用到这个库，仿真的时候注销掉。 --library UNISIM; --use UNISIM.VComponents.all; --------------------------------------- entity counter8bit is port(cnt_inout: inout std_logic_vector(7 downto 0); rst, up_down, enb, load, clk: in std_logic); end counter8bit; architecture Behavioral of counter8bit is signal cnt_in, cnt_out: std_logic_vector(7 downto 0); begin --产生三态缓冲器 process(load, cnt_out) begin if (load=0) then cnt_inout=(OTHERS=Z); cnt_in=cnt_inout; else cnt_in=(OTHERS=Z); cnt_inout=cnt_out; end if; end process; --三态缓冲计数器 process(rst, clk) begin if (rst=1) then cnt_out=(OTHERS=0); elsif( clkevent and clk =1) then if load=0 then cnt_out=cnt_in; else if (enb=1) then if (up_down=0) then cnt_out=cnt_out+1; else cnt_out=cnt_out-1; end if; --end up_down else cnt_out=cnt_out; end if; --end enb end if; --end load end if; --end rst end process; ---------------------------------------------------- -----综合时，数据流端加上拉电阻，要用到这些命令，建test bench时注销掉。 -- U0: PULLUP port map (O = cnt_inout(0)); -- U1: PULLUP port map (O = cnt_inout(1)); -- U2: PULLUP port map (O = cnt_inout(2)); -- U3: PULLUP port map (O = cnt_inout(3)); -- U4: PULLUP port map (O = cnt_inout(4)); -- U5: PULLUP port map (O = cnt_inout(5)); -- U6: PULLUP port map (O = cnt_inout(6)); -- U7: PULLUP port map (O = cnt_inout(7)); ----------------------------------------------------- end Behavioral;RTL Schematic VHDL Test Bench -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_lo