《电子技术数字基础 Digital Fundamentals》双语课件PPT-第07章 触发器 Latches, Flip-Flops and Timers.ppt

7 Latches, Flip-Flops and Timers Contents Latches (锁存器) Edge-triggered Flip-Flops （边沿触发器） Master-Slave Flip-Flops （主从触发器） Flip-Flop Operating Characteristics （触发器动作特点） Flip-Flop Function Expression （触发器特性方程） 7-0 Introduction A flip-flop (触发器） or latch is a digital circuit that has two outputs Q and , which always in the opposite states. 7-0 Introduction Unlike the gates studied up to this point, the flip-flop can in some states maintain its output state (on or off) after the input signals which produced the output state change. It can store the information or the states. In this chapter, bistable (双稳态), monostable (单稳态), and astable (暂态，非稳态) logic devices are covered. 7-1 Latches （锁存器）- the basic S-R (set-reset) latch （基本RS 触发器） A latch is a type of bistable logic device. An active-HIGH input S-R latch is formed with two cross-coupled NOR gates. An active-LOW input S-R latch is formed with two cross-coupled NAND gates. 7-1-1 The Basic S-R Latch Two versions of S-R latches 7-1-1 The Basic S-R Latch Logic diargram and its operation principle 7-1-1 The Basic S-R Latch Set operation 7-1-1 The Basic S-R Latch No change condition 7-1-1 The Basic S-R Latch 7-1-1 The Basic S-R Latch Invalid 7-1-1 The Basic S-R Latch 7-1-1 The Basic S-R Latch Two possibilities for the SET operation 7-1-1 The Basic S-R Latch Two possibilities for the RESET operation 7-1-1 The Basic S-R Latch No change condition. 7-1-1 The Basic S-R Latch Truth table for an active-LOW input SR latch (特性表） 7-1-1 The Basic S-R Latch Logic symbols for the SR latches 7-1-1 The Basic S-R Latch EX. Determine the output waveform according to the input waveforms for a crossed NAND SR latch, and Q starts in the RESET (LOW) state. 7-1-1 The Basic S-R Latch EX. 7-1-1 The Basic S-R Latch For a S-R latch, it has no enable input (使能端）, or clock control pin （时钟端）, so the SET and RESET inputs can change the output states directly. In this case, the SET and RESET inputs are a