利用vhdl设计乘法器implementofmultiplierby-中华科技大学.pdfVIP

Journal of China Institute of Technology Vol.29-2003.12 利用 VHDL設計乘法器 Implement of Multiplier by Using VHDL 許地申 Dih-Shen Hsu 中華技術 學院電機系副 教授 Associate Professor Department of Electrical Engineering China Institute of Technology 摘 要 在計算機結構裡加，減，乘，除是常被用到的運算， 本文提出以非常高速積 體電路硬體描述語言 (VHDL)來描述硬體，說明如何將兩個運算元作相乘的運算。 我們首先以無號數整數做乘法運算來說明其原理設計其電路結構， 。其實在 VHDL 程式中，我們更可以載入 STD_LOGIC_ARITH 與 STD_LOGIC_UNSIGNED 元 件盒之後，直接進行乘法運算，既簡單又容易擴充。最後，我們將以 4-bit X 4-bit 的例子來做電路描述、電路合成、電路模擬並以七段顯示器將其結果顯示出來。 關鍵字 ：非常高速積體電路硬體描述語言 、電路描述、電路合成 、電路模擬 Abstract We have known operation that perform addition, subtraction, multiplication, and division. In this paper we are presented primarily to describe hardware using by VHDL. We can explain how multiplication may be performed for two operand. Multiplication of unsigned numbers illustrates the main issues involved in the design of multiplier circuit. In fact, after the STD_LOGIC_ARITH and STD_LOGIC_UNSIGNED packages were added to the VHDL program, it became not only simple but also easy to extended. Next, consider a 4 x 4 example to circuit description, circuit synthesis, and circuit simulation by using VHDL. Finally, this approach can also be displayed by 7-segment. Keyword : VHDL , circuit description , circuit synthesis, circuit simulation - 1 - 利用 VHDL設計乘法器 壹.簡介 VHDL是