16位加法计数器的设计.docVIP

目录 摘要 I Abstract II 1 绪论 1 2 计数器的工作原理 2 3 设计原理 3 3.1 整体设计思想 3 3.2 单元模块的设计 4 3.3 顶层模块（整体电子线路系统）的设计 8 4 电路系统的功能仿真 12 5 硬件调试 14 6 个人小结 16 参考文献 17 摘要 计数器是数字系统中使用较多的一种时序逻辑器件。计数器的基本功能是统计时钟脉冲的个数，即对脉冲实现计数操作。计数器也可以作为分频、定时、脉冲节拍产生器和脉冲序列产生器使用。计数器的种类很多，按构成计数器中的各触发器是否使用一个时钟脉冲源来分，可分为同步计数器和异步计数器；按进位体制的不同，可分为二进制计数器、十进制计数器和任意进制计数器；按计数过程中数字增减趋势的不同，可分为加法计数器、减法计数器和可逆计数器；还有可预制数和可编计数器等等。本次课程设计将利用众多集成电路软件软件中的Quartus II软件，使用VHDL语言编程来设计一个可通过3个选择位M2、M1、M0实现最多8种不同模式的计数方式的16位二进制加法计数器，并把程序下载到相关可编程逻辑器件（如Cyclone系列的EP1C3T144C8型号芯片），结合相关外围电路来实现硬件的调试。调试结果表明，所设计的计数器正确实现了5、10、16、46、100、128、200、256进制，共8种可选计数模式的计数功能。 关键词：二进制；计数器；VHDL语言 Abstract The The counter is used in digital systems, a kind of more temporal logic devices. Counter is the basic function of the number of statistical clock pulse, namely to pulse realize counting operation. Counter can also act as a separate frequency, timing, pulse beats generator and pulse sequence generator use. A lot of more phyletic, according to counter the constitute counter each toggle whether to use a clock pulse source to points, can be divided into synchronous counter and asynchronous counter, According to the binary system of different, can be divided into binary counter, decimal counter and arbitrary disables counter, According to count process of digital increase or decrease trend is different, can be divided into addition and subtraction counter and counter reversible counter, There can be prefabricated number and programmable counter etc. This paper will introduce using numerous EDA (electronic design automation) in software Quartus II software, use VHDL language programming to design a by 3 choice a M2, M1 and M0 achieve maximum count of 8 different mode of 16 bit binary counter way, and the program download to related programmable logic devices (such as the Cyclone series EP1C3T100C8 model chip), unifies the related peripheral device to realize the principle of hardware debugging method. Keywords: binary; Counter; VHDL language 1 绪论 现代电子设计技术的核心已日趋转向基