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crais:a crossbar-based interconnection scheme on fpga for big data
Wang C, Li X, Zhou XH. CRAIS: A crossbar-based interconnection scheme on FPGA for big data. JOURNAL OF COM-
PUTER SCIENCE AND TECHNOLOGY 30(1): 84–96 Jan. 2015. DOI 10.1007/s11390-015-1506-5
Chao Wang (王 超),
Xi Li (李 曦), , and
Xue-Hai Zhou (周学海),
E-mail: cswang, llxx, xhzhou@
Received July 15, 2014; revised December 12, 2014.
On-chip interconnection has posed significant challenges in multiprocessor system on chip (MPSoC) design
paradigm, especially in big data era. With respect to the state-of-the-art, crossbar-based interconnection methodologies
are still efficient for FPGA-based small-scale heterogeneous MPSoCs. This paper proposes a crossbar-based on-chip inter-
connection scheme, named CRAIS. CRAIS utilizes reconfigurable crossbar interconnections between microprocessors and
intellectual property (IP) cores in MPSoC. The hardware interconnection can be dynamically reconfigured during execution.
Empirical results on FPGA prototype demonstrate that CRAIS can achieve more than 7X speedup compared with the
state-of-the-art StarNet approach, while it only utilizes 21%35% hardware resources of StarNet.
interconnect, big data, crossbar, multiprocessor system on chip
. Not only the existed volume but also the
generation speedup of data is tremendous, and requires
With the wide application of cloud computing, high-speed data transfer.
mobile Internet and networking, social and enter- .
prise big data pervades our daily life. Diversely, the The efficiency of data mining should be maintained.
vast amounts of data generated at an explosion-like Above
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