低功耗高速缓存无效缓存路访问混合过滤机制研究.PDF

∗ 1,2+ 1,5 3 1 4 灵 , 远 , 东 , 娄 1( , 100190) 2 ( , 100049) 3( ,) 4 (,, 100190) 5(,,,100048) Low Power Cache Architectures with Hybrid Approach of Filtering Unnecessary * Way Accesses 1,2+ 1,5 3 1 4 FAN Ling-Jun , XU Yuan-Chao , SHI Wei-Song , FAN Dong-Rui , LOU Jie 1(State Key Laboratory of Computer Architecture, ICT, CAS, Beijing 100 190, China) 2 (Graduate University of Chinese Academy of Sciences, Beijing, 100049, China) 3(Department of Computer Science, Wayne State University, Detroit MI-48202, USA) 4 (Intel Corporation, Beijing, 100190, China) 5(College of Information Engineering, Capital Normal University, Beijing 100048, China) + Corresponding author: Phn: +86- 10-6260061 1, Fax: +86- 10 E-mail: fanlingjun@ Received 20 12-07-04; Accepted 2012-09- 16 Abstract : Power has been a big issue in processor design for several years. As caches account for more and more CPU die area and power, this paper presents using filtering unnecessary way accesses to reduce dynamic power consumption of caches shared by instruction and data. Our methods include using Invalid Filter, which could eliminate accesses to cache ways contained invalid blocks, and I/D Filter, which could eliminate accesses to cache ways contained instruction/data access type mismatch blocks, and Tag-2 Filter, which could eliminate accesses to cache ways contained tag lowest 2 bits mismatch blocks. Since the methods reducing the activities happened in cache architecture, dynamical CPU power could be significantly decreased. In the paper, we also propose combing the above methods together, which is called Invalid+I/D+Tag-2 Filter, in an attempt to achieve better power saving results. Our evaluations show that, we could obtain 19.6%-47.8