EDA技术实用教程(第二版)潘松黄继业第2版第9章_VHDL基本语句.pptVIP

BEGIN PROCESS(clk) VARIABLE crcvar : std_logic_vector(5 DOWNTO 0); BEGIN IF(clkevent AND clk = 1) THEN IF(st = 0 AND datald = 1) THEN dtemp = sdata; sdatam = sdata; cnt = (OTHERS = 0); hsend = 0; st = 1; ELSIF(st = 1 AND cnt 7) THEN cnt = cnt + 1; IF(dtemp(11) = 1) THEN crcvar := dtemp(11 DOWNTO 6) XOR multi_coef; dtemp = crcvar(4 DOWNTO 0) dtemp(5 DOWNTO 0) 0; ELSE dtemp = dtemp(10 DOWNTO 0) 0; END IF; ELSIF(st=1 AND cnt=7) THEN datacrco=sdatam dtemp(11 DOWNTO 7); hsend = 1; cnt = cnt + 1; E