并行处理与体系结构hitsz-lec08-review2.ppt

* Memory Hierarchy Review 2 Outline 7.4 Virtual Memory Address Mapping Key Design Issues Page Table Page Faults Translation lookaside buffer (TLB) Protection with Virtual Memory 7.5 Common Framework Four question Miss rates with setassociative and cache size Three misses 7.6 Modern memory hierarchies 7.8 Concluding Remark 7.4 Virtual Memory Main memory can act as a cache for the secondary storage (disk) Motivation To allow efficient and safe sharing of memory among multiple programs. Allow a single user program to exceed the size of primary memory Previous solution: programmers divided programs into pieces, called overlays Advantages: illusion of having more physical memory program relocation protection 7.4 Address Mapping for Virtual Memory Virtual address Physical address Page : blocks of memory Page in disk 7.4 Mapping From Virtual to Physical Pages: virtual memory blocks Virtual address space=232 =4GB Physical address space=230=1GB 7.4 Key Design Issues in VM Pages should be large enough to amortize the high access time huge miss penalty, thus pages should be fairly large E.g 32-64KB pages Reduce the page fault rate full-associative placement Page fault penalty takes millions of cycles can handle the faults in software instead of hardware Use clever algorithm to replace pages while page faults occur. E.g. LRU (least recently used) Use write-back instead of write-through using write-through is too expensive so we use write-back 7.4 Page Tables Page tables are used to located pages by using a full table that indexes the memory Because full-associative placement to locate a entry is difficult Page tables are stored in main memory, each program has its own page table 7.4 Page Tables Page table is indexed with the virtual page number to obtain the corresponding portion of the physical address Example: Page size : 212 = 4 KB, number of page entry: 220 = 1 million entries Page entry only need 19 bits, other bits are used to store additional information,