EDA课程设计-电子钟.doc

EDA 电 子 钟 设 计 学院 班级 学号 姓名 一，设计要求 设计一个电子时钟，要求可以显示时、分、秒，用户可以设置时间。 扩展功能要求：跑表功能，闹钟功能，调整数码管的亮度。 二、VHDL代码 -------分频------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fenpin is port ( clk : in std_logic;--10m频 clk_10000 : out std_logic;--1000分频 clk_100 : out std_logic;--100k分频 clk_1 : out std_logic--10m分频 ); end entity; architecture one of fenpin is signal Q_1 : integer range 0 to 500; signal Q_2 : integer range 0 to 50000; signal Q_3 : integer range 0 to 5000000; signal clk10000 : std_logic; signal clk100 : std_logic; signal clk1 : std_logic; begin fen1000:process(clk) begin if clkevent and clk=1 then if Q_1=500 then Q_1 = 0; clk10000 = not clk10000; else Q_1=Q_1+1; end if; end if; end process; fen100k:process(clk) begin if clkevent and clk=1 then if Q_2=50000 then Q_2 = 0; clk100= not clk100; else Q_2=Q_2+1; end if; end if; end process; fen10m:process(clk) begin if clkevent and clk=1 then if Q_3=5000000 then Q_3 = 0; clk1=not clk1; else Q_3=Q_3+1; end if; end if; end process; clk_10000 = clk10000; clk_100 = clk100; clk_1 = clk1; end one; ------走表------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clock is port(clk_1:in std_logic; key8:in std_logic; hs_set,hg_set,ms_set,mg_set,ss_set,sg_set:in integer range 0 to 9; hs_out,hg_out,ms_out,mg_out,ss_out,sg_out:out integer range 0 to 9); end entity; architecture bhv of clock is signal shi:integer range 0 to 100; signal fen:integer range 0 to 100; signal miao:integer range 0 to 100; begin process(clk_1,key8,hs_set,hg_set,ms_set,mg_set,ss_set,sg_set) begin if key8=1 then shi=hs_set*10+hg_set; fen=ms_set*10+mg_set; miao=ss_set*10+sg_set; elsif clk_1event and clk_1=1 then if miao=59 then miao=0; fen=fen+1; elsif fen59