EDA技术实用教程第六章_VHDL设计进阶.pptVIP

6.4.3 三态总线电路设计 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY tristate2 IS port ( input3, input2, input1, input0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); enable : IN STD_LOGIC_VECTOR(1 DOWNTO 0); output : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END tristate2 ; ARCHITECTURE multiple_drivers OF tristate2 IS BEGIN PROCESS(enable,input3, input2, input1, input0 ) BEGIN IF enable = 00 THEN output = input3 ; ELSE output =(OTHERS = Z); END IF ; IF enable = 01 THEN output = input2 ; ELSE output =(OTHERS = Z); END IF ; IF enable = 10 THEN output = input1 ; ELSE output =(OTHERS = Z); END IF ; IF enable = 11 THEN output = input0 ; ELSE output =(OTHERS = Z); END IF ; END PROCESS; END multiple_drivers; 【例6-15】 6.4.3 三态总线电路设计 图6-17 例6-15错误的综合结果 6.4.3 三态总线电路设计 library ieee; use ieee.std_logic_1164.all; entity tri is port (ctl : in std_logic_vector(1 downto 0); datain1， datain2，datain3， datain4 : in std_logic_vector(7 downto 0); q : out std_logic_vector(7 downto 0) ); end tri; architecture body_tri of tri is begin q = datain1 when ctl=00 else (others =Z) ; q = datain2 when ctl=01 else (others =Z) ; q = datain3 when ctl=10 else (others =Z) ; q = datain4 when ctl=11 else (others =Z) ; end body_tri; 【例6-16】 6.4.3 三态总线电路设计 图6-18 例6-16正确的综合结果 6.4.4 顺序条件语句IF语句 （1）IF 条件句 Then 顺序语句 END IF ; （2）IF 条件句 Then 顺序语句 ELSE 顺序语句 END IF ; （3）IF 条件句 Then IF 条件句 Then ... END IF END IF （4）IF 条件句 Then 顺序语句 ELSIF （5）顺序语句 IF 条件句 Then ... ELSE 顺序语句 END IF 6.4.4 顺序条件语句IF语句 【例6-17】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY control_stmts IS PORT (a, b, c: IN BOOLEAN; output: OUT BOOLEAN); END control_stmts; ARCHITECTURE example OF control_stmts IS BEGIN PROCESS (a, b, c) VARIABLE n: BOOLEAN; BEGIN IF a THEN