基于FPGA的嵌入式CPU设计.doc

摘 要 随着EDA技术的快速发展，基于FPGA的嵌入式微处器的应用越来越广泛。同时使用超高速集成电路硬件描述语言(VHDL)和基于现场可编程逻辑阵列(FPGA)来设计电路的方法也得到迅速的完善。FPGA的嵌入式系统具有设计周期短、产品上市速度快、设计风险和成本低、集成度高、灵活性大、维护和升级方便、硬件缺陷修复和排除简单等优点。 本文基于FPGA设计一个16位的中央处理器(CPU)，先从CPU的结构和工作原理出发，提出两种设计方案。一种是使用流水线技术的精简指令集的CPU(即RISC CPU)，另一种不使用流水线技术的RISC CPU。通过分析可以知道第一种方案可以达到较高的工作效率和执行速度，但实现起具有一定的难度。第二种方案实现比较简单，但难以达到工作频率和执行速度较高的设计目标。因此，设计采用流水线技术设计。这个CPU具有16位的地址总线和数据总线，并且采用了5级流水线来提高CPU的工作效率。该流水线CPU由取指令(IF)、指令译码和读寄存器文件(ID)、执行或计算地址(EXE)、存储器访问(MEM)、回写(WB)五个部分组成。 CPU的各部件利用VHDL语言和EDA工具设计实现的，采用自顶向下的设计方法。EDA工具使用了Altera公司的Quartus II 5.0设计软件。 关键词 中央处理器，精简指令集，流水线 Abstract With the rapid development of EDA ( Electronic Design Automation ) technology, the processor of embedded system based on FPGA is researched and used widely. The method which uses VHDL language( Very High Speed Integrated Circuit Description Language ) and FPGA to design electric circuit in the meantime also gets quickly perfect. The embedded system which designs according to the FPGA has short period for design, and the product appear on market quickly. Useing this way to design can make cost be lower, and the products will be high integration and flexibility. The supportion is convenient. Upgrade and eliminate errors is easy. This paper introduces the design of a 16- bit RISC CPU. It can design in two ways. The first one is uses the Pipeline technique, but the second don’t. Useing the Pipeline technology can make CPU work quickly and efficiency, but the design will be more difficult. For the high speed and efficiency, this design adoption Pipeline technique to designs a 16-bit RISC CPU. Its instruction length is 16 bits, applied 5 class Pipelines. The processor designed was a traditional five stage pipeline design. The stages were Instruction Fetch, Instruction Decode, Execute, Memory Access, and Write Back. The 16-bit RISC CPU was implemented using VHDL and TOP-DOWN. EDA tool use the software of Quartus II 5.0 of the altera company. Key Words Central Processing Unit, Reduced Instruction, Pipe