一讲HDL语言概述.pptVIP

module test_mux2;//无输入输出端口 reg A,B,Sel; wire Out; mux2 m(Out,A,B,Sel); initial begin A=0;B=1;Sel=0; #10 B=0; #10 B=1; Sel=1; #10 A=1; #10 $stop; end initial begin $monitor($time,“ Out=%b, A=%b, B=%b, Sel=%b, Out,A,B,Sel); end endmodule module test_compare; reg [1:0] a,b; //测试激励信号a,b wire equal; compare c(equal,a,b); initial begin a=2’b00;b=2’b00; #10 a=2’b01; #10 b=2’b01; #10 a=2’b10; #10 b=2’b10; #10 a=2’b11; end initial begin $monitor($time,“ a=%b, b=%b, equal=%b ”, a,b,equal); end endmodu