High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic 细粒度的动态高吞吐量的异步管道.pptVIP

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High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic 细粒度的动态高吞吐量的异步管道.ppt

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High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic 细粒度的动态高吞吐量的异步管道

High-ThroughputAsynchronous Pipelines forFine-Grain Dynamic Datapaths Montek Singh and Steven Nowick Columbia University New York, USA {montek,nowick}@ /~montek Outline Introduction Background: Williams’ PS0 pipelines New Pipeline Designs Dual-Rail: LP3/1, LP2/2 and LP2/1 Single-Rail: LPSR2/1 Practical Issue: Handling slow environments Results and Conclusions Why Dynamic Logic? Potentially: Higher speed Smaller area “Latch-free” pipelines: Logic gate itself provides an implicit latch lower latency shorter cycle time smaller area –– very important in gate-level pipelining! Our Focus: Dynamic logic pipelines How Do We Achieve High Throughput? Introduce novel pipeline protocols: specifically target dynamic logic reduce impact of handshaking delays shorter cycle times Pipeline at very fine granularity: “gate-level:” each stage is a single-gate deep highest throughputs possible latch-free datapaths especially desirable dynamic logic is a natural match Prior Work: Asynchronous Pipelines Sutherland (1989), Yun/Beerel/Arceo (1996) very elegant 2-phase control ? expensive transition latches Day/Woods (1995), Furber/Liu (1996) 4-phase control ? simpler latches, but complex controllers Kol/Ginosar (1997) double latches ? greater concurrency, but area-expensive Molnar et al. (1997-99) Two designs: asp* and micropipeline ? both very fast, but: asp*: complex timing, cannot handle latch-free dynamic datapaths micropipeline: area-expensive, cannot do logic processing at all! Williams (1991), Martin (1997) dynamic stages ? no explicit latches! ? low latency throughput still limited Background Introduction Background: Williams’ PS0 pipelines New Pipeline Designs Dual-Rail: LP3/1, LP2/2 and LP2/1 Single-Rail: LPSR2/1 Practical Issue: Handling slow environments Results and Conclusions PS0 Pipelines (Williams 1986-91) Basic Architecture: PS0 Function Block Each output is produced using a dynamic gate: Dual-Rail Completion Detector OR together two rails of each