基于FPGA的数字通信实现多路数据时分复用和解复用系统系统.docVIP

摘 要 本设计实现多路数据时分复用和解复用系统。设计分为发端和收端，以FPGA作为主控核心。发端系统有三路并行数据输入：A/D转换数据，拨码开关1路和拨码开关2路。这三路数据在FPGA的控制下作为串行码分时输出。发端FPGA包括分频模块、复用模块和电压显示模块。在收端，串行数据进入FPGA，并由FPGA提取位时钟，识别帧同步并解复用发端打包的三路码。收端的FPGA包括数字锁相环模块、解复用模块和电压显示模块。发端FPGA输入有三路8-bit数据：第一路为A/D数据、第二路和第三路是拨码开关产生的数据，另外插入一路巴克码。这四路码组成一帧，由FPGA对其时分复用。A/D输入端的模拟信号的电压值通过FPGA处理，显示在数码管上。在收端，FPGA首先提取位同步，然后识别帧同步，一旦识别出帧同步，FPGA分别解复用三路数据。本文详细阐述了此系统的设计方法，制作过程以及制作过程中的问题。设计者的工作包括：系统各部分电路元件的确定、确定系统框图、画出系统原理图、根据原理图设计FPGA的RTL代码、综合、仿真RTL代码、设计PCB板和在线调试FPGA功能。 关键字：数字锁相环；帧同步；时分复用；Verilog HDL语言；串行A/D变换； Abstract The system is designed for data multiplexed and de-multiplexed. It is based on TDM. The system includes the transmitter and the receiver. They are implemented mainly by FPGA. There are three inputs in the transmission system: data from A/D converter, DIP1 and DIP2. The three channels are out serially and time-divisional under the FPGA’s control. The FPGA in the transmitter is divided into four modules which are frequency divider, Barker generator, data multiplexer and voltage display. Voltage display is used for processing the data converted by ADC and sending it to the LED. The serial data are serial shifted into the FPGA in the receiver. Bit-synchronize and frame-synchronize are both picked up, and then de-multiplex. The FPGA in the receiver is divided into three modules which are digital PLL, data de-multiplexer and voltage display. The transmitter will multiplex four ways of 8-bit parallel data. The first way is ADC data, the second and the third way is generated by dip-key. The other is Barker code used for frame synchronizing. The receiver will maintain the bit synchronizing, recognize one frame and de-multiplex three ways data. The essay will discuss the design progress, the programming idea and some problems. Works have to be done by the designer are: Specify all system components, Make system specification, Draw system schematics, Write RTL code according the schematics, Synthesis and simulate the RTL code, Design the PCBs, Validate th