第三讲反相器第三讲反相器.ppt

* For class. response determined mainly by the output capacitance of the gate, CL - drain diffusion capacitance of the NMOS and PMOS transistors; the connecting wires, and the input capacitances of the fan-out gates A fast gate is built either by keeping the output capacitance small or by decreasing the on-resistance or the transistor (or both) Decreasing the on-resistance achieved by increasing the W/L ratio of the device Be award that the on-resistance of the NMOS and PMOS transistors is not constant; rather it is a nonlinear function of the voltage across the transistor * A high gain in the transition region is VERY desirable. In the extreme case of an infinite gain, the noise margins simplify to VOH – VM and VM – VOL for NMH (ideally, VDD – VM) and NML (ideally, VM – GND), respectively, and span the complete voltage swing. * Note: simulation overestimates the gain – as seen on the next slide, the maximum gain (at VM) is only -17 And piece-wise linear approximation model is optimistic wrt noise margins. Low output resistance is a good measure of the sensitivity of the gate wrt noise induced at the output and should be as low as possible. * A good device has a small oxide thickness (-3nm), a small length (-25nm), a higher width (+30nm) and a smaller threshold (-60mV). The opposite is true for a bad device. * Not the best curve for 0.5 supply (but the best I could do in ppt). Observations The gain of the inverter in the transition region increases with a reduction in Vdd. For a fixed r, VM is proportional to Vdd. At a voltage of 0.5V (just 100mV above the threshold of the transistors) the width of the transition region measures only 10% of the supply voltage (and a gain of -35), while it widens to 17% for 2.5V But, reducing the supply Is absolutely detrimental to the performance of the gate The dc characteristics become increasingly sensitive to variations in the device parameters (e.g., VT) Scaling the supply means reduced signal swing making the gate mo