一个老外写的DDS(VHDL)的例子,很经典。.docVIP

典。 -- DDFS.vhd--------------------------------------- Direct Digital Freq. Synthesis ----------------------------------------- (c) Bert Cuzeau, ALSE - info@-- May be reproduced provided that copyright above remains.-- We use one of the symetries in the sine function,-- so the lookup table is re-used twice (128 entries table)-- The Sine Table is built by a C program...--------------------------------------- Design IOs :-- Clk : Global Clock input-- Rst : Global Reset input-- Freq_data : 8-bit frequency control vector-- from DIP switches on the board.-- Dout : is signed 8-bit output to the DAC.-- -----------------------------------------------library IEEE;use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;-- -----------------------------------------------Entity DDFS is-- -----------------------------------------------Port ( CLK : in std_logic;RST : in std_logic;Freq_Data : in std_logic_vector (7 downto 0);Dout : out std_logic_vector (7 downto 0));end DDFS;-- -----------------------------------------------Architecture RTL of DDFS is-- -----------------------------------------------signal Address : unsigned (6 downto 0);signal Result : std_logic_vector (7 downto 0);signal Accum : unsigned (28 downto 0); -- we want very low Frequencies !signal Sign : std_logic;begin-- Signed Accumulator-- ------------------Acc: process (CLK,RST)beginif RST=1 thenAccum 0);elsif rising_edge(CLK) thenAccum = Accum + unsigned(Freq_Data);end if;END process acc;Sign = Accum(Accumhigh); -- MSB-- Lookup Table Index calculation-- ------------------------------Address = unsigned(Accum(Accumhigh-1 downto Accumhigh-Addresslength));-- SINE Look-Up TABLE-- --------------------- Inference of an Asynchronous Rom.-- A synchronous one would be better, but we register the output.-- This table has been built by GENVEC.exe (C program)-- We use only positive values ! (sign comes from quadrant info)-- This could be further optimized by coding only one