《EDA技术》习题(解答).docVIP

《EDA技术》习题 5 习 题 5-1 归纳利用Quartus II进行VHDL文本输入设计的流程从文件输入一直到SignalTap II测试。1 建立工作库文件夹和编辑设计文件2 创建工程3 编译前设置4 全程编译5 时序仿真引脚锁定配置文件下载打开SignalTap II编辑窗口调入SignalTap II待测信号SignalTap II参数设置SignalTap II参数设置文件存盘SignalTap II测试编译下载启动SignalTap II进行采样与分析SignalTap II的其他设置和控制方法 5-2 由图5-40和图5-41，详细说明工程设计CNT10的硬件工作情况。图5-40工程设计CNT10的工作情况图5-41工程设计CNT10的工作情况 5-3 如何为设计中的SignalTap II加入独立采样时钟?试给出完整的程序和对它的实测结果。SignalTap II提供独立时钟的方法是在顶层文件的实体中增加一个时钟输入端口，如语句:LOGC_CLK:IN STD_LOGIC;在此实体中不必对其功能和连接具体定义，而在SignalTap II的参数设置中则可以选择LOGC_CLK为采样时钟。 5-4 参考QuartusII的Help，详细说明Assignments菜单Settings对话框的功能。 (1)说明其中的Timing RequirementsQptions的功能、他用方法和检测途经。Specifying Timing Requirements and Options (Classic Timing Analyzer) You can specify timing requirements for Classic timing analysis that help you achieve the desired speed performance and other timing characteristics for the entire project, for specific design entities, or for individual clocks, nodes, and pins. When you specify either project-wide or individual timing requirements, the Fitter optimizes the placement of logic in the device in order to meet your timing goals. You can use the Timing wizard or the Timing Analysis Settings command to easily specify all project-wide timing requirements, or you can use the Assignment Editor to assign individual clock or I/O timing requirements to specific entities, nodes, and pins, or to all valid nodes included in a wildcard or assignment group assignment. To specify project-wide timing requirements: On the Assignments menu, click Settings. In the Category list, select Timing Analysis Settings. To specify project-wide tSU, tH, tCO, and/or tPD timing requirements, specify values under Delay requirements. To specify project-wide minimum delay requirements, specify options under Minimum delay requirements. Under Clock Settings, select Default required fmax. In the Default required fmax box, type the value of the required fMAX and select a time unit from the list. If you want to specify options for cutt