21.UART控制器.PDFVIP

21. UART控制器 November 2012 cv_54021-1.2 cv_54021-1.2 硬核处理器系统 (HPS) 对异步串行通信提供两个UART 控制器。UART 控制器基于工业标 ® ® 准 16550 UART 控制器。UART 控制器是 Synopsys DesignWare APB 通用异步接收器 / 发射器 (DW_apb_uart) 外围的实例。 UART 控制器功能 UART 控制器提供以下功能性和功能： ■ 可编程的字符属性，例如每字符的数据位数，可选的奇偶校验位和结束位数 ■ 换行符生成和检测 ■ 直接存储器访问 (DMA)控制器接口 ■ 优先的中断识别 ■ 可编程的 baud速率 ■ 假起始位检测 ■ 每 16750标准的自动流程控制模式 ■ 内部环回模式支持 ■ 128-bit 发送和接收FIFO 缓冲器深度 ■ FIFO 缓冲器状态寄存器 ■ FIFO缓冲器访问模式(用于FIFO缓冲器测试)使能主器件进行的接收FIFO缓存器 的写入和主器件进行的发送 FIFO 缓冲器的读取 ■ 映射寄存器减少软件开销并且提供可编程的复位 ■ 发送器保持寄存器空 (THRE) 中断模式 © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at /common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Alteras standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications