CPLD课程设计代码.docVIP

附：程序代码 注：译码器，分频，点阵，流水灯，步进电机五部分为源代码的功能拓展，带下划线部分为修改或添加的代码。 交通灯，多路选择器为编写设计代码。 1、译码器： LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY decoder3_8 IS PORT( A,B,C: IN STD_LOGIC; Y :OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --段选输出 en :OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); --位选输出 END decoder3_8; ARCHITECTURE fun OF decoder3_8 IS SIGNAL indata: STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN indata =CBA; encoder: PROCESS(indata ) BEGIN CASE indata IS WHEN 000=Yen WHEN 001=Yen WHEN 010=Yen WHEN 011=Yen WHEN 100=Yen WHEN 101=Yen WHEN 110=Yen WHEN 111=Yen WHEN OTHERS=Yen END CASE; END PROCESS encoder; END fun; 2、分频： library ieee; use ieee.std_logic_1164.all; entity div_f is port(clk :in std_logic; miao_out :out std_logic; f_miao_out:out std_logic; fourhz :out std_logic; -- 4Hz 输出 halfhz :out std_logic; --0.5Hz输出 en :out std_logic); end div_f; architecture miao of div_f is begin en=1; p1:process(clk) variable cnt:integer range 0 to 3999999; variable ff:std_logic; begin if clkevent and clk=1 then if cnt3999999 then cnt:=cnt+1; else cnt:=0; ff:=not ff; end if; end if; miao_out=ff; end process p1; p2:process(clk) variable cnn:integer range 0 to 1999999; variable dd:std_logic; begin if clkevent and clk=1 then if cnn1999999 then cnn:=cnn+1; else cnn:=0; dd:=not dd; end if; end if; f_miao_out=dd; end process p2; ------------p3：4Hz生成部分-------------- p3:process(clk) variable cnt0:integer range 0 to 999999; variable aa:std_logic; begin if clkevent and clk=1 then if cnt0999999 then cnt0:=cnt0+1; else cnt0:=0; aa:=not aa; end if; end if; fourhz=aa; end process p3; --------p4：0.5Hz生成部分------------- p4:process(clk) variable cnn0:integer range 0 to 7999999; variable bb:std_logic; be