246 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II EXPRESS….pdfVIP

246 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 52, NO. 5, MAY 2005 A Low-Voltage 10-Bit CMOS DAC in 0.01-mm2 Die Area Brandon Greenley, Raymond Veith, Dong-Young Chang, and Un-Ku Moon Abstract—A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18- m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 m 94 m die area. A segmented R-2R ar- chitecture is used for the DAC core in order to maximize matching accuracy for a minimal use of die area. A pseudocommon centroid layout is introduced to overcome the layout restrictions of con- ventional common centroid techniques. A linear current mirror is proposed in order to achieve linear output current with reduced voltage headroom. The measured differential nonlinearity by integral nonlinearity (DNL/INL) is better than 0.7/0.75 LSB and 0.8/2 LSB for 1.8-V and 1.4-V power supplies, respectively. The DAC remains monotonic ( DNL 1 LSB) as INL reaches 4 LSB down to 1.3-V operation. The DAC consumes 2.2 mA of current at all supply voltage settings. Index Terms—Die area, digital–analog (D/A), digital-to-analog conversion (DAC), low voltage. Fig. 1. The 10-bit segmented architecture. II. DESIGN CONSIDERATIONS I. INTRODUCTION A. Architecture IGITALLY cont