VHDL计时器程序.docVIP

library ieee; use ieee.std_logic_1164.all; entity clkgen is port(clk:in std_logic; newclk:out std_logic); end entity clkgen; architecture art of clkgen is signal cnter:integer range 0 to 10#29999#; begin process(clk) is begin if clkevent and clk=1 then if cnter=10#29999# then cnter=0; else cnter=cnter+1; end if; end if; end process; process(cnter) is begin if cnter=10#29999# then newclk=1; else newclk=0; end if; end process; end architecture art; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt6 is port(clk:in std_logic; clr:in std_logic; ena:in std_logic; cq:out std_logic_vector(3 downto 0); carry_out:out std_logic); end entity cnt6; architecture art of cnt6 is signal cqi:std_logic_vector(3 downto 0); begin process(clk,clr,ena) is begin if clr=1 then cqi=0000; elseif clkevent and clk=1 then if ena=1 then if cqi=0101 then cqi=0000; else cqi=cqi+1; end if; end if; end if; end process; cq=cqi; end architecture art; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt10 is port(clk:in std_logic; clr:in std_logic; ena:in std_logic; cq:out std_logic_vector(3 downto 0); carry_out:out std_logic); end entity cnt10; architecture art of cnt10 is signal cqi:std_logic_vector(3 downto 0); begin process(clk,clr,ena) is begin if clr=1 then cqi=0000; elseif clkevent and clk=1 then if ena=1 then if cqi=1001 then cqi=0000; else cqi=cqi+1; end if; end if; end if; end process; process(cqi) is begin if cqi=0000 then carry_out=1; else carry_out=0; end if; end process; cq=cqi; end architecture art; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY TIMES IS