Chapter 2 Architecture Overview TI C5000官方课件.ppt

Copyright ? 2003 Texas Instruments. All rights reserved. DSP C5000 Chapter 2 Architecture Overview Objectives Describe and compare the basic CPU architecture of the C54x and the C55x Discuss pipeline phases List the key features of the C54x and C55x memory map and peripherals Give a detailed presentation of CPU registers What Makes a DSP a Special Processor? Common Architectural Features of DSPs Common Architectural Features of DSPs General DSP System Block Diagram What Constitutes a Good DSP? DSP Requires Multiply and Accumulate Multiply and Accumulate Unit Multiple Buses Internal Memory for Fast Access Instruction Pipeline for Fast Execution Sequential Processing of Instructions Less Cycles per InstructionLess Power Consumption Texas InstrumentsC5000 Solutions Basic Harvard Architecture1st DSP Generation TMS320C54X DSP Generation Block Diagram TMS320C54X Key Features C54X Memory Blocks Memory 192K words × 16-bit addressable memory space in 3 blocks: 64K-words program** 64K-words data, 64K-words I/O **extended program memory depending on the C54X version. TMS320C55X DSP Block Diagram TMS320C55x Key Features More C55x Features User-configurable IDLE Domains Variable length instructions and efficient block repeat operations Dual MAC operations in a single cycle Performs high precision arithmetic and logical operations Shift a 40-bit result up to 31 bits to the left,or 32 bits to the right Performs arithmetic in a simpler ALU of 16 bits. Hold results of computations and reduce the required memory traffic (4 Accumulators) Comparison Between C54x and C55x Performances Features Comparison Between C54x and C55x Same family but big differences! Short overview of the C54x and C55x Convolution with the C54x 1 of 2 Convolution with the C54x 2 of 2 With the C55x it can be done faster! C54x Architecture C55x Architecture C55x Program and Instruction Units C55x Addressing Unit (AU) C55x Data Computation Unit (DU) C55x Writes (E and F buses) C54x Block Diagra