Design and simulation of a smart ratiometric ASIC chip for VOC monitoring -main--巩文亮精选.pdfVIP

Sensors and Actuators B 95 (2003) 232–243 Design and simulation of a smart ratiometric ASIC chip for VOC monitoring ´ a b a,∗ a Jesús Garcıa-Guzmán , Nicola Ulivieri , Marina Cole , Julian W. Gardner a School of Engineering, University of Warwick, Coventry CV4 7AL, UK b Department of Information Engineering, Universita’ di Siena, 53100 Siena, Italy Abstract This paper reports on the design and simulation of a novel ratiometric application specific integrated circuit (ASIC) chip for the monitoring of volatile organic compounds (VOCs) or gases. The design integrates two polymeric chemoresistors in a ratiometric configuration, together with smart circuitry, into a single chip fabricated through a standard silicon CMOS process. The circuit provides automatic compensation of signal from variations in both supply voltage and ambient temperature. On-chip control of the operating temperature of the sensors is also an option. The response of the ratiometric set of polymeric chemoresistors to different concentrations of gases at different temperatures and humidities was simulated with the aid of a novel parametric Cadence model. Simulations confirm that the ratiometric configuration is less sensitive to temperature variations and that it also has a better performance in terms of humidity dependence when compared to an individual chemoresistor. These features, together with its ability to compensate for a large range in values of polymer resistance, make us believe that the circuit offers relevant smart capabilities at a very low-cost and so it can be used as the main component for t