电子技术课程的设计指导书程序.docVIP

电子技术课程设计指导书第二部分 基本实验 实验1基本逻辑门电路的VHDL设计 设计程序 12 输入与非门的 VHDL 描述 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY nand2_lab1 IS PORT(a, b : IN STD_LOGIC; y: OUT STD_LOGIC); END nand2_lab1; ARCHITECTURE one OF nand2_lab1 IS BEGIN y= a nand b; END one; 2. 2输入或门的 VHDL 描述 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY or2_lab IS PORT(a, b : IN STD_LOGIC; y: OUT STD_LOGIC); END or2_lab; ARCHITECTURE one OF or2_lab IS BEGIN y= a or b; END one; 3. 非门的 VHDL 描述 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY hnot IS PORT(a : IN STD_LOGIC; y: OUT STD_LOGIC); END hnot; ARCHITECTURE one OF hnot IS BEGIN y= not a; END one; 4异或门的 VHDL 描述 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY xor2_lab IS PORT(a, b : IN STD_LOGIC; y: OUT STD_LOGIC); END xor2_lab; ARCHITECTURE one OF xor2_lab IS BEGIN y= a xor b; END one; 实验2组合逻辑电路的VHDL设计 设计程序 18-3编码器的 VHDL 描述 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY encoder83 IS PORT( d : IN STD_LOGIC_VECTOR(7 DOWNTO 0); encode: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END encoder83; ARCHITECTURE one OF encoder83 IS BEGIN encode = 111 when d(7) = 1 else 110 when d(6) = 1 else 101 when d(5) = 1 else 100 when d(4) = 1 else 011 when d(3) = 1 else 010 when d(2) = 1 else 001 when d(1) = 1 else 000 when d(0) = 1 ; END one; 2. 3线-8线通用译码器的 VHDL 描述 LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY decoder IS  PORT(a,b,c : IN STD_LOGIC; G1,G2a,G2b : IN STD_LOGIC;  Y : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END decoder; ARCHITECTURE decoder_arc OF decoder IS  SIGNAL indata : STD_LOGIC_VECTOR (2 DOWNTO 0);