《高性能处理器体系结构》Review of Instruction Sets,Pipelines指令集，管道.ppt

* * I n s t r. O r d e r Time (clock cycles) add r1,r2,r3 sub r4,r1,r3 and r6,r1,r7 or r8,r1,r9 xor r10,r1,r11 IF ID/RF EX MEM WB ALU Im Reg Dm Reg ALU Im Reg Dm Reg ALU Im Reg Dm Reg Im ALU Reg Dm Reg ALU Im Reg Dm Reg Data Hazard Solution: Forwarding “Forward” result from one stage to another  * * MEM/WR ID/EX EX/MEM Data Memory ALU mux mux Registers NextPC Immediate mux What circuit detects and resolves this hazard? HW Change for Forwarding * * Reg Time (clock cycles) lw r1,0(r2) sub r4,r1,r3 IF ID/RF EX MEM WB ALU Im Reg Dm ALU Im Reg Dm Reg Forwarding (or Bypassing): What about Loads? Dependencies backwards in time are hazards Data Hazard Even with Forwarding Can’t solve with forwarding ，Must delay/stall instruction dependent on loads * * Reg Time (clock cycles) lw r1,0(r2) sub r4,r1,r3 IF ID/RF EX MEM WB ALU Im Reg Dm ALU Im Reg Dm Reg Stall Forwarding (or Bypassing): What about Loads ? Dependencies backwards in time are hazards Data Hazard Even with Forwarding Can’t solve with forwarding ，Must delay/stall instruction dependent on loads * * Try producing fast code for a = b + c; d = e – f; assuming a, b, c, d ,e, and f in memory. Slow code: LW Rb,b LW Rc,c ADD Ra,Rb,Rc SW a,Ra LW Re,e LW Rf,f SUB Rd,Re,Rf SW d,Rd Software Scheduling to Avoid Load Hazards Fast code: LW Rb,b LW Rc,c LW Re,e ADD Ra,Rb,Rc LW Rf,f SW a,Ra SUB Rd,Re,Rf SW d,Rd Compiler optimizes for performance. Hardware checks for safety. * * I: sub r4,r1,r3 J: add r1,r2,r3 K: mul r6,r1,r7 Three Generic Data Hazards Write After Read (WAR) InstrJ writes operand before InstrI reads it Called an “anti-dependence” by compiler writers.This results from reuse of the name “r1”. Can’t happen in DLX 5 stage pipeline because: All instructions take 5 stages, and Reads are always in stage 2, and Writes are always in stage 5 * * I: sub r1,r4,r3 J: add r1,r2,r3 K: mul r6,r1,r7 Three Generic Data Hazards Write After Write (WAW