VHDL与数字集成电路设计VHDL7-1.pptVIP

* * * 2 Phase, with multiple conditional buffered clocks 2.8 nF clock load 40 cm final driver width Local clocks can be gated “off” to save power Reduced load/skew Reduced thermal issues Multiple clocks complicate race checking trise = 0.35ns tskew = 50ps tcycle= 1.67ns EV6 (Alpha 21264) Clocking 600 MHz – 0.35 micron CMOS Global clock waveform * * * Two Phase Handshake * EE141 * EE141 * * * D Clk Q D Q Clk tc-q thold PWm tsu td-q Delays can be different for rising and falling data transitions T * D Clk Q D Q Clk tc-q thold T tsu Delays can be different for rising and falling data transitions