毕业论文-基于fpga的万年历程序设计说明书.docVIP

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clock is port(rst:in std_logic; clk:in std_logic; clr:in std_logic; display_mode: in std_logic; inc:in std_logic; mode:in std_logic; seg8:out std_logic_vector(7 downto 0); scan:out std_logic_vector(7 downto 0); led:out std_logic_vector(3 downto 0) ); end; architecture one of clock is --signal state:std_logic_vector(2 downto 0); --signal dis_mode:std_logic_vector(1 downto 0); signal state:integer range 0 to 7; signal dis_mode:integer range 0 to 3; --signal qhh,qhl,qmh,qml,qsh,qsl,qy1,qy2,qy3,qy4,qm