[工学]VHDL_附2_Xilinx软件操作.pptVIP

View Synthesis Report * 5. Simulation * Implementation Behavioral Simulation 6. New Simulation Source Right Click New Source * * * * * A B C Z 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 Left Click - Invert Pattern Wizard Right Click - Edit Value * * 6.5 New VHDL Test Bench * * * * 7. Xilinx ISE Simulator * 1) Right Click 2) Run Simulation Result * A B C Z 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 * 实验1.2 一位全加法器的设计 要求： 1)题目：设计一位全加法器，它包括两个输出：总和（Ｓ）和进位输出（Co）,以及输入Ａ、Ｂ和进位输入（Ci）。真傎表如下： Ａ Ｂ Ｃi S Co 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 2)给出真傎表或表达式 3)给出VHDL程序 4)给出仿真波形的建立与仿真结果 * Ａ Ｂ Ｃi S Co 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 * * Ａ Ｂ Ｃi S Co 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 RLT View * * WUHAN UNIVERSITY OF TECHNOLOGY ruanjun@whut.edu.cn Ruan Jun ruanjun@whut.edu.cn WUHAN UNIVERSITY OF TECHNOLOGY WUHAN UNIVERSITY OF TECHNOLOGY ruanjun@whut.edu.cn Ruan Jun WUHAN UNIVERSITY OF TECHNOLOGY ruanjun@whut.edu.cn Ruan Jun WUHAN UNIVERSITY OF TECHNOLOGY ruanjun@whut.edu.cn Ruan Jun WUHAN UNIVERSITY OF TECHNOLOGY ruanjun@whut.edu.cn Ruan Jun WUHAN UNIVERSITY OF TECHNOLOGY ruanjun@whut.edu.cn Ruan Jun WUHAN UNIVERSITY OF TECHNOLOGY ruanjun@whut.edu.cn Ruan Jun Xilinx ISE * Introduction Computer Aided Design (CAD) software makes it easy to implement a desired logic circuit by using a programmable logic device, such as a field-programmable gate array (FPGA) chip. * FPGA CAD flow * involves the following basic steps: Design Entry – the desired circuit is specified either by using a hardware description language, such as Verilog or VHDL, or by means of a schematic diagram(原理图) Synthesis – the CAD Synthesis tool synthesizes the circuit into a netlist that gives the logic elements (LEs) needed to realize the circuit and the connections between the LEs Functional Simulation – the synthesized circuit is tested to veri