[工学]Web_信息检索pc_chap2.ppt

Chapter 2Parallel Programming Platforms Limitation of memory system performance 程序执行的效率不仅依赖于processor 的速度，也依赖内存的速度 A memory system consists of DRAM and multiple levels of catches. Example 2.2 CPU 1 GHz(109), two add units and can execute four instructions in each cycle, add time = 4 G Dram access time 100 ns (= 100 cycles), processor must wait 100 ns before it can process the data A?B= a1b1+a2b2+,…,+anbn, 实际每次取数需100ns, 实际峰值为1G/100=100M ,大大低与运算峰值。解决方法是用catch把block的数据读到快速缓存中。 Strided access 在存储空间上交叉取数据 Dichotomy(二分法） of parallel computing platforms 按控制结构分 SIMD (single instruction, multiple data stream) A singe control unit dispatches instruction to each processing units 早期采用的体系结构,典型的机器有 Illiac IV, MPP, CM-2, Pentium’SSE(streaming SIMD extensions) 为专用计算设计的, e.g., 图像处理, 排序,…, MIMD (Multiple instruction, multiple data stream) Different control unit dispatches instruction to different processing units Dichotomy of parallel computing platforms 逻辑上分：从程序设计角度，从通讯方式上分 基于信息通讯；基于共享地址空间 基于物理相互连接方式 Mesh,hypercube SIMD的特点 在同一时间，所以的处理器执行同一指令，但对应不同的数据。 The variable activity mask (0,1) is used to control a processor whether to implement the instruction or not. If the central control unit is divided into n different control units, the model becomes a MIMD (multiple instruction multiple data streams) 基于通讯Communication Model of Parallel Platforms Shared-address-space platforms Note: The address-space is shared in logic, while the term of shared memory means to chare memory by physic circuits or network, the latter is the special case of the former. Global or local Uniform memory access (UMA) Shared memory（the acces time is the same） non-uniform memory access(NUMA) Distributed shared memory Send(ID,Info); receive(ID,Info) （by message passing） Crossbar network The interconnection network consisting of the processing elements and memory bank. The switch on the nodes of network will determine if to access the data storing in the banks. The number of switches is O(pb), where p the