[信息与通信]Latch-up_in_MOS_IC.pdfVIP

O2Micro Proprietary Specification 5/17/2010 Latch-up prevention in CMOS IC – 2nd version 5/17/2010 Author: Marian Spenea 1. Scope To present effective and practical methods to prevent the latch-up effect in CMOS ICs. Content: • The latch-up effect in CMOS IC; • Methods to prevent the Latch-up effect; • Design rules implementation for latch-up prevention; • Simulation results of different latch-up triggering conditions; 2. The latch-up effect in CMOS IC 2.1 The latch-up effect. The latch-up effect is defined as the creation of a low impedance current path between the power supply (VDD) and the GND of an IC, by triggering of bipolar structures. The parasitic bipolar transistors intrinsically included in every NMOS (NPN) and PMOS (PNP) structure can interact in certain circumstances and create a low impedance current path, as shown in the Figure 1. The bipolar transistors themselves can cause latch-up as well. Once the base-emitter junction of QP or QN transistor is forward biased, the positive feedback will finally bring both bipolar transistors in saturation. Once they reach this state, the trigger signal is not needed anymore, which means that a true latched state is self-sustaining. The voltage across the latched structure is roughly 2 V, which represents the sum between a collector-emitter saturation voltage and a base-emitter saturation voltage. The current is limited by the size of the two transistors and the parasitic resistors across the current path. Unless the supply current is limited to a small value, the chip overheats and the internal metal lines are melted due to over-current effect. Secondary effects may then appear and finally the IC becomes totally unusable.