[工学]lecture3_2_RTL Combinational Circuit.pptVIP

RTL design RTL design 3 types of modeling used for RTL design: Behavior modeling (always block) data flow modeling (operators) structural modeling (module instantiation) A digital circuit consists of two kinds of elements: Combinational logic: output is the function of input Sequential logic: output is the function of input state Both of them can be constructed using RTL design RT-Level Combinational Circuit Consists of adders, comparators, multiplexers, etc. implemented by: Operators : data flow Always block : behavior If statement: behavior Case statement: behavior Operators Operators Operators Operators Operators Operators Operators Operators Operators Operators Operator precedence Always block for a combinational circuit The focus of this section is on the synthesis of combinational circuits and we limit the discussion to three types of statements: Blocking procedural assignment If statement Case statement Always block for a combinational circuit Basic syntax and behavior Always block for a combinational circuit An always block can be considered as a complex circuit part. It can be suspended or activated. When any signal of the sensitivity list changes or an event occurs, the part is activated and executes the internal procedural statements. Since there is no other timing control construct, the execution continues to the end and the part is suspended. Thus, an always block actually loops forever and the initiation of each loop is controlled by the sensitivity list. Procedural assignment Example1, blocking assignment Data types for procedural assignment Blocking/non-blocking assignment- basic rules of application Sensitivity list In verilog 2001 always @ (a, b, c) always @ * In verilog 1995 always @ (a or b or c) Procedural assignment vs. continuous assignment Procedural assignment vs. continuous assignment example Common errors in combinational circuit codes a Variable assigned in multiple always blocks a Incomplete sensi