64进制BCD码计数器VHDL设计.docVIP

实验名称：实验六 时序逻辑VHDL设计——计数器 二、64进制BCD码VHDL设计 1.实体框图 2.程序设计 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CDU_64A IS PORT(CLK:IN STD_LOGIC; Q22:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); Q11:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END CDU_64A; ARCHITECTURE AA OF CDU_64A IS SIGNAL COUT2,COUT1:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK) BEGIN IF(CLKEVENT AND CLK=1)THEN IF(COUT2=6 AND COUT1=3)THEN COUT2=0000;COUT1=0000; ELSIF(COUT1=9)THEN COUT2=COUT2+1;COUT1=0000; ELSE COUT2=COUT2;COUT1=COUT1+1;