verilog 秒表.docVIP

module watch(clk,out_wei,out_duan,rst,key2); //key2==27pin input rst; input clk; input key2; output [5:0]out_wei; output [7:0]out_duan; reg [5:0]out_wei=6b000000; reg [7:0]out_duan=8 //a b c d e f g dp reg [4:0]count; reg [3:0]count1; reg [14:0]count2; reg [7:0]sec_l=8 //zero at first reg [7:0]sec_h=8 reg [7:0]fen_l=8 reg [7:0]fen_h=8 reg [7:0]msec_l=8 reg [7:0]msec_h=8 reg [3:0]s_1=0; reg [3:0]s_2=0; reg [3:0]s_3=0; reg [3:0]s_4=0; reg [3:0]s_5=0; reg [3:0]s_6=0; reg clk_out; reg pause;//信号 always@(posedge clk) begin //fenpin if(count2==25000) begin //one of thousand secend 25000 count2=0; clk_out=~clk_out; end else count2=count2+1; end always@(posedge clk_out) begin //scan count=count+1b1; case(count) 1 :begin out_wei=6b111110; out_duan=msec_l; end 3:begin out_wei=6b111101; out_duan=msec_h; end 6:begin out_wei=6b111011; out_duan=sec_l; end 9:begin out_wei=6b110111; out_duan=sec_h; end 12:begin out_wei=6b101111; out_duan=fen_l; end 15:begin out_wei=6b011111; out_duan=fen_h; end 18:count=0; endcase end always@(negedge key2) begin pause=~pause; end always@(posedge clk_out or negedge rst) begin //minite secend if(!rst) begin s_1=0; s_2=0; s_3=0; s_4=0; s_5=0; s_6=0; end else if(count1==10)begin //if 1s l+1 count1=0; if(s_6==9) begin s_6=0; if(s_5==9) begin s_5=0; if(s_1==9) begin s_1=0; if(s_2==5) begin s_2=0; if(s_3==9) begin s_3=0; if(s_4==5) s_4=0; else s_4=s_4+1; end else s_3=s_3+1; end else s_2=s_2+1; end else s_1=s_1+1; end else s_5=s_5+1; end else s_6=s_6+1; end else if(pause==1) begin c