[信息与通信]ADSP_TS201S.pdfVIP

• TigerSHARC® a Embedded Processor ADSP-TS201S KEY FEATURES KEY BENEFITS Up to 600 MHz, 1.67 ns instruction cycle rate Provides high performance static superscalar DSP 24M bits of internal—on-chip—DRAM memory operations, optimized for telecommunications 25 mm × 25 mm (576-ball) thermally enhanced ball grid infrastructure and other large, demanding multiprocessor array package DSP applications Dual-computation blocks—each containing an ALU, a Performs exceptionally well on DSP algorithm and I/O multiplier, a shifter, a register file, and a communications benchmarks (see benchmarks in Table 1) logic unit (CLU) Supports low overhead DMA transfers between internal Dual-integer ALUs, providing data addressing and pointer memory, external memory, memory-mapped peripherals, manipulation link ports, host processors, and other Integrated I/O includes 14-channel DMA controller, external (multiprocessor) DSPs port, four link ports, SDRAM controller, programmable Eases DSP programming through extremely flexible