[工学]EDA技术与应用讲义 第9章第2节 Quartus II中的设计优化.pptVIP

第9章第2节 Quartus II中的优化设计配置、仿真和报告EDA技术与应用 课程讲义 下一章 本节内容 时序分析的基本概念和术语 Quartus II中的时序约束设置 Quartus II中的时序分析 Quartus II中的编译报告 FPGA芯片的时序指标举例 有关时序分析更多的资料请参见/quartushelp/list.jsp?keyword=verificationanalysis 时序分析的基本概念和术语 时钟建立时间(tSU:clock setup time) 时钟保持时间(th:clock hold time) 时钟输出延时(tCO :Clock to output delay) 时钟偏斜（ Clock Skew） 引脚到引脚的延时(tPD: Pin-to-Pin Delay) 时序裕量（Slack） 独立时钟和衍生时钟（Absolute Clock Derived Clock） 占空比（Duty Cycle） 行波时钟（Ripple Clock） 建立时间 和 保持时间 tSU (clock setup time) tH (clock hold time) tCO (Clock to output delay) 时钟偏斜（clock skew）:图示 时钟偏斜（clock skew） The difference in the arrival time of a clock signal at two different registers, which can be caused by path length differences between two clock paths, or by using gated or rippled clocks. Clock skew is the most common cause of internal hold violations, as shown in figure 1 引脚间延时tPD (pin-to-pin delay) The time required for a signal from an input pin to propagate through combinational logic and appear at an external output pin. In the Quartus??II software, you can specify the required tPD for the entire project and/or for any input pin, output pin, bidirectional pin. You can also assign a point-to-point tPD assignment to specify the required delay between an input pin and a register, a register and a register, a register and an output pin. 时序裕量（Slack） Slack is the margin by which a timing requirement was met or not met. A positive slack value, displayed in black, indicates the margin by which a requirement was met. A negative slack value, displayed in red, indicates the margin by which a requirement was not met. Slack time is calculated using the following equation: slack = required maximum P2P time - actual maximum P2P time Timing Analyzer Summary 独立时钟和衍生时钟（absolute clock derived clock） 概念： absolute clock 不依赖于其他时钟信号而存在的时钟 derived clock 由某个absolute clock 经过相移、分频、倍频而得到的时钟 时序分析的处理： 一个设计可以允许有多个独立时钟存在 只对一个独立时钟内相关的所有信号进行时序分析 占空比（Duty cycle (%) ） Indicate