单元9-6步进马达转速控制实习.ppt

VHDL數位電路實習與專題設計 * 單元9-6 步進馬達轉速控制實習 ? 程式與說明 步進馬達轉速控制程式碼 12 entity stepmotor_speed is 13 port( 14 clk : in std_logic; 15 spd : in std_logic_vector(3 downto 0); 16 step: out std_logic_vector(3 downto 0) 17 ); 18 end stepmotor_speed; 19 20 architecture arch of stepmotor_speed is 21 signal buf: std_logic_vector (4 downto 0); 22 signal dly : std_logic; 23 signal clk_new: std_logic; 24 signal cnt : std_logic_vector(1 downto 0); 25 begin 26 ---------- process --------- 27 process(clk) 28 begin 29 if clkevent and clk=1 then 30 dly = buf(4); 31 buf = buf +(0 spd); 32 end if; 33 end process; 34 clk_new=(buf(4) xor dly) and not clk; 35 process(clk_new) 36 begin 37 if clk_newevent and clk_new=1 then 38 cnt = cnt+1; 39 end if; 40 end process; 41 step = 1000 when cnt=0 else 42 0100 when cnt=1 else 43 0010 when cnt=2 else 44 0001; 45 end arch; 陳慶逸、林昱翰編著---文魁資訊 VHDL數位電路實習與專題設計 * 單元9-6 步進馬達轉速控制實習 程式與說明 除頻器程式碼（將1.8432MHz除頻產生50Hz輸出）： 13 entity clk_div_step is 14 generic(divisor:integer:=36864); 15 port( 16 clk_in : in std_logic; 17 clk_out: out std_logic 18 ); 19 end clk_div_step; 20 21 architecture arch of clk_div_step is 22 signal cnt2 : std_logic; 23 begin 24 ---------- clk divider ---------- 25 process(clk_in) 26 variable cnt1,divisor2 : integer range 0 to divisor; 27 begin 28 divisor2:=divisor/2; 29 ----- up counter ----- 30 if (clk_inevent and clk_in=1) then 31 if cnt1 = divisor then 32 cnt1 := 1; 33 else 34 cnt1 := cnt1 + 1; 35 end if; 36 end if; 37 ----- clk_out register clk generator ----- 38 if (clk_inevent and clk_in=1) then 39 if (( cnt1 = divisor2) or (cnt1 = divisor))then 40 cnt2 = not cnt2 ; 41 end if; 42 end if; 43 clk_out = cnt2 ; 44 end process; 45 end arch; 46 陳慶逸、林昱翰編著---文魁資訊 VHDL數位電路實習與專題設計 * ?