[信息与通信]VHDL参考资料.doc

VHDL快速参考手册PRIMARY DESIGN UNIT MODEL STRUCTURE Each?VHDL design unit comprises an entity declaration and one or more architectures. Each architecture defines a different implementation or model of a given design unit. The entity definition defines the inputs to, and outputs from the module, and any generic parameters used by the different implementations of the module. Entity Declaration Format ??? entity? name? is ??????? port( port definition list );-- input/output signal ports ??????? generic( generic list);?? -- optional generic list ??? end name; Port declaration format:port_name: mode data_type; Themodeof a port defines the directions of the singals on that pirt, and is one of: in, out, buffer, or inout. Port Modes: An in port can be read but not updated within the module, carrying information into the module. (An in port cannot appear on the left hand side of a signal assignment.) An out port can be updated but not read within the module, carrying information out of the module. (An out port cannot appear on the right hand side of a signal assigment.) A buffer port likewise carries information out of a module, but can be both updated and read within the module. An inout port is bidirectional and can be both read and updated, with multiple update sources possible. ? NOTE: A buffer is strictly an output port, i.e. can only be driven from within the module, while inout is truly bidirectional with drivers both within and external to the module. Example ?? entity counter is ??????? port (Incr, Load, Clock: in???? bit; ????????????? Carry:???????????? out??? bit; ????????????? Data_Out:????????? buffer bit_vector(7 downto 0); ????????????? Data_In:?????????? in???? bit_vector(7 downto 0)); ?? end counter; Generics allow static information to be communicated to a block from its environment for all architectures of a design unit. These include timing information (setup, hold, delay times), part sizes, and other parameters. Example ??? entity and_gate is ?