vhdl ch11 VHDL 设计要点.pptVIP

FPGAVHDL Design Tips Dealing With Clock Problems Use Only Dedicated Clock Nets for Clock Signals Do Not Put Any Logic in Clock Nets Traditional Clock Divider Introduces clock skew between CLK1 and CLK2 Uses an extra BUFG to reduce skew on CLK2 Recommended Clock Divider No clock skew between flip-flops Avoid Clock Glitches Because flip-flops in today’s FPGAs are very fast, they can respond to very narrow clock pulses Never source a clock signal from combinatorial logic Also known as “gating the clock” Avoid Clock Glitches This circuit creates the same function, but it creates the function wit