数字逻辑设计与VHDL描述第２版徐惠民安德宁第七章.ppt

北京邮电大学 huimin@bupt.edu.cn * 一般时序电路分析设计 例7.23 用VHDL语言对101序列检测器进行数据流描述。 ENTITY detector_101 IS PORT (x, clk : IN BIT; z : OUT BIT); END detector_101; ARCHITECTURE dataflow OF detector_101 IS TYPE state IS (A, B, C); TYPE state_vector IS ARRAY (NATURAL RANGE ) OF state; FUNCTION one_of (sources: state_vector) RETURN state IS BEGIN RETURN sources(sources’LEFT); END one_of; SIGNAL current : one_of state REGISTER := A; 北京邮电大学 huimin@bupt.edu.cn * 一般时序电路分析设计 BEGIN cc: BLOCK (clk =1 AND NOT clkSTABLE) BEGIN s1: BLOCK (current = A AND GUARD) BEGIN current = GUARDED B WHEN x=1 ELSE A; END BLOCK s1; s2: BLOCK (current = B AND GUARD) BEGIN current = GUARDED C WHEN x=0 ELSE B; END BLOCK s2; s3: BLOCK (current = C AND GUARD) BEGIN current = GUARDED B WHEN x=1 ELSE A; z = 1 WHEN (current = C AND x = 1) ELSE 0; END BLOCK s3; END BLOCK cc; END dataflow; 北京邮电大学 huimin@bupt.edu.cn * 一般时序电路分析设计 例7.24 对例7.22的时序机用VHDL语言进行顺序描述。 ENTITY detector_2 IS PORT ( clk, A, B: IN STD_LOGIC; Z: OUT STD_LOGIC ); END; 北京邮电大学 huimin@bupt.edu.cn * 一般时序电路分析设计 ARCHITECTURE behav OF detector_2 IS TYPE SREG_TYPE IS (INIT, A0, A1, A00, A11); SIGNAL sreg: SREG_TYPE; BEGIN PROCESS (clk) BEGIN IF clk EVENT AND clk = 1 THEN CASE sreg IS WHEN INIT = IF A=0 THEN sreg = A0; ELSIF A=1 THEN sreg = A1; END IF; WHEN A0 = IF A=0 THEN sreg = A00; ELSIF A=1 THEN sreg = A1; END IF; WHEN A00 = IF A=0 THEN sreg = A00; ELSIF A=1 AND B=0 THEN sreg = A1; ELSIF A=1 AND B=1 THEN sreg = A11; END IF; 北京邮电大学 huimin@bupt.edu.cn * 电位型触发器 WHEN A1 = IF A=0 THEN sreg = A0; ELSIF A=1 THEN sreg = A11; END IF; WHEN A11 = IF A=0 AND B=0 THEN sreg = A0; ELSIF A=0 AND B=1 THEN sreg = A00; ELSIF A=1 THEN sreg = A11;