VHDL双语教学第2章教材教学课件.pptVIP

VHDL Simulation Synthesis (Design Flow / Language Framework) Agenda Design Example Basic Language Framework Majority Voter Circuit Output ‘1’ of there is more ‘1’s than ‘0’s Output ‘0’ of there is more ‘0’s than ‘1’s 多数表决器 Schematic CPLD VHDL Description library ieee; use ieee.std_logic_1164.all; --------------------------------- entity XYZ is -- Can put anything after the ‘--’ port ( A1, A2, A3 : in std_logic; F : out std_logic ); end XYZ; --------------------------------- architecture XYZ _arch of XYZ is begin F = (A1 and A2) or (A2 and A3) or