液晶cell的结构Array_Process_(_Module).ppt

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液晶cell的结构Array_Process_(_Module).ppt

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液晶cell的结构Array_Process_(

? Color Filter on Array ( COA) Panel Design Section / Technology Division HannStar Confidential Data line BM Insulator (SiNx) Pixel ITO Align Margin Aperture ? Color Filter on Array ( COA) Panel Design Section / Technology Division HannStar Confidential Data line (BM) Insulator (SiNx) Aperture Pixel ITO Organic Insulator ITO electrode Pixel Structure of TFT LCD Introduction to TFT Array Processing Glass Substrate Glass Substrate Cs on Common 與 Cs on Gate 架構液晶畫素 TFT Gate Line Data Line Cs Cs 液晶畫素 TFT Common Common Gate Line Data Line Cs Cs Cs on Common Cs on Gate PEP5 : ITO 1.Process Flow : 5000 ITO Pre-Clean 5100 ITO Sputter 5600 ITO Wet Etch 5500 Photo 5800 PR Strip PEP5 TFT CF BM Pixel structure Pixel dimension: 72.5 x 217.5 (μm2) Size of transistor is W/L = (13/13) Due to Al gate process Stable TFT performance Aperture Ratio: ~ 54% PEP1 PEP2 PEP3 PEP4 PEP5 BM Tandem repairing circuit Tandem repairing circuit Laser welding to short the adjacent pixels 1 Introduction to TFT Array Processing 5PEP TFT Procdess ---- 1PEP : Gate Layer Formation Glass Substrate Gater TFT MIM Cs PAD 5PEP TFT Procdess ---- 2PEP :Stopper Formation Glass Substrate I stopper(SiNx ) Channel layer(a-Si) Gate Insulator(SiNx) Gate Insulator(SiOx) Gate(Al-Nd/Mo) TFT MIM Cs PAD Introduction to TFT Array Processing 5PEP TFT Procdess ---- 3PEP : Island Singal line 5PEP TFT Procdess ---- 4PEP : THPassivation TFT MIM Cs PAD TFT MIM Cs PAD Signal layer(Mo/Al/Mo) S/D layer(N+ a-Si) I stopper(SiNx ) Channel layer(a-Si) Gate Insulator(SiNx) Gate Insulator(SiOx) Gate(Al-Nd/Mo) Passivation Signal layer(Mo/Al/Mo) S/D layer(N+ a-Si) I stopper(SiNx ) Channel layer(a-Si) Gate Insulator(SiNx) Gate Insulator(SiOx) Gate(Al-Nd/Mo) Introduction to TFT Array Processing 5PEP TFT Procdess ---- 5PEP : Pixel (ITO) TFT MIM Cs PAD Signal layer(Mo/Al/Mo) Passivation Pixel layer(ITO)