[工学]基于QUARTUS MODELSIM 仿真.docVIP

基于QUARTUS MODELSIM 仿真 建立MODELSIM ALTERA库文件 在transcript窗键入如下命令即可建立名为cycloneii的modelsim ALTERA仿真文件。 vlib cycloneii vmap cycloneii cycloneii vcom -work cycloneii C:/altera/80/quartus/eda/sim_lib/cycloneii_atoms.vhd vcom -work cycloneii c:/altera/80/quartus/eda/sim_lib/cycloneii_components.vhd vcom -work cycloneii c:/altera/80/quartus/eda/sim_lib/altera_mf_components.vhd vcom -work cycloneii c:/altera/80/quartus/eda/sim_lib/altera_mf.vhd 注：220model.vhd 是work.lpm_components 本例中名字命名为了cyclone  因为原来在D:\MODALT\cycloneii下编译的quartus的仿真库，所以在新的工程中将库映射到D:\MODALT\cycloneii，库名为cyclone 注意引用仿真库时库名叫cyclone。 设计源文件： 见附录 测试台文件 LIBRARY cyclone ; LIBRARY ieee ; USE IEEE.STD_LOGIC_SIGNED.ALL; USE cyclone.cycloneii_components.all ; USE ieee.std_logic_1164.all ; ENTITY wave_tb IS END ; -- cyclone为MODELSIM中ALTERA库的名称 ARCHITECTURE wave_tb_arch OF wave_tb IS SIGNAL dout : std_logic_vector (7 downto 0) ; SIGNAL dac_wr : std_logic ; SIGNAL dac_cs : std_logic ; SIGNAL switch : std_logic_vector (2 downto 0):=000 ; SIGNAL dac_ab : std_logic ; SIGNAL clk : std_logic:=0 ; COMPONENT wave PORT ( dout : out std_logic_vector (7 downto 0) ; dac_wr : out std_logic ; dac_cs : out std_logic ; switch : in std_logic_vector (2 downto 0) ; dac_ab : out std_logic ; clk : in std_logic ); END COMPONENT ; BEGIN DUT : wave PORT MAP ( dout = dout , dac_wr = dac_wr , dac_cs = dac_cs , switch = switch , dac_ab = dac_ab , clk = clk ) ; process(clk) begin clk =not clk after 10 ns; end process; END ; 设计文件选择由QUARTUS生成的WAVE.VHO，由WAVE.VHO为源生成并编辑WAVE_TB.VHD文件，仿真WAVE_TB文件 在transcript窗键入 Vsimadd wave * Vsimrun 140us  选择dout信号，选择format-analog，REDIX-UNSIGNED 附录： 设计源文件 LIBRARY IEEE, cyclone; USE IEEE.STD_LOGIC_SIGNED.ALL; USE IEEE.std_logic_1164.all; USE cyclone.cycloneii_components.all; ENTITY wave IS PORT ( dac_wr : OUT