实验2——算数运算电路实验.doc

《专用集成电路设计基础》电路设计实验 实验1——算数运算电路实验 （实用型移位式二进制乘法器电路） 电路功能 设计一个移位式乘法器电路，要求： 采用最简单的方式产生部分积； 采用右移部分积之和的部分积求和累加方式； 需要有独立的乘积寄存器。 电路设计 采用Verilog HDL硬件描述语言进行，用ModelSim EDA软件进行仿真。 实用型移位式乘法器电路描述： //******************************************************************// //****** MODULE DESCRIPTION : 16-Bit Practical Shift Multiplier //****** AUTHOR : rzH //****** DATE : 06.20.2013 //******************************************************************// module multiplier_nbit ( rst, clk, x, y, result ); //data width definition parameter mwidth = 16; parameter rwidth = mwidth + mwidth; // input rst, clk; //input operation data x and y input [mwidth-1:0] x, y; //output multiply result output [rwidth-1:0] result; reg [rwidth-1:0] result; //stcnt: state counter---3 state //state 0: input data registered //state 1: multiply operation //state 2: output data registered reg [1:0] stcnt; //mucnt: multiply step counter---16 step reg [3:0] mucnt; //multiplicand register reg [mwidth-1:0] opx; //partial product register //also to save resource, multiplier are initially //stored in the low 16bit of the register reg [rwidth-1:0] ptpro; //select data source to multiplicand register wire tx_sel; //select data source to partial product register wire [1:0] tp_sel; //select data source to ptadd according to //the lowest bit of the multiplier in multiply process wire adp_sel; wire [rwidth-1:0] ptshf1, ptshf0, ptadd; //partial product initial wire [rwidth-1:0] ptini; //temprory wire [mwidth-1:0] temp_x; reg [rwidth-1:0] temp_p; //output multiply result enable wire mout_en; //16-bit adder output: summary and carry wire [mwidth-1:0] sum; wire co; //stcnt state 1: start multiply process assign mucnt_en = (stcnt == 2b01) ? 1b1 : 1b0;