电子技术课程设计报告参考.docVIP

电子技术课程设计报告 必选题（一）： 7段LED译码显示电路设计 一、程序代码: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DECLED IS PORT(CLK:IN STD_LOGIC; DOUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END DECLED; ARCHITECTURE behav OF DECLED IS SIGNAL CNT4B:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK) BEGIN IF CLKEVENT AND CLK=1 THEN CNT4B=CNT4B+1; END IF; END PROCESS; PROCESS(CNT4B) BEGIN CASE CNT4B IS WHEN 0000 = DOUT =; WHEN 0001 = DOUT =; WHEN 0010 = DOUT =; WHEN 0011 = DOUT =; WHEN 0100 = DOUT =; WHEN 0101 = DOUT =; WHEN 0110 = DOUT =; WHEN 0111 = DOUT =; WHEN 1000 = DOUT =; WHEN 1001 = DOUT =; WHEN 1010 = DOUT =; WHEN 1011 = DOUT =; WHEN 1100 = DOUT =; WHEN 1101 = DOUT =; WHEN 1110 = DOUT =; WHEN 1111 = DOUT =; WHEN OTHERS = DOUT =; END CASE; END PROCESS; END behav; 二、时序仿真结果: 必选题（二）： 数字频率计设计 一、程序代码: 1、 十进制计数器CNT10 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY CNT10 IS PORT(CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; ENA:IN STD_LOGIC; CQ:OUT INTEGER RANGE 0 TO 15; CARRY_OUT:OUT STD_LOGIC); END CNT10; ARCHITECTURE behav OF CNT10 IS SIGNAL CQI:INTEGER RANGE 0 TO 15; BEGIN PROCESS(CLK,CLR,ENA) BEGIN IF CLR=1 THEN CQI=0; ELSIF CLKEVENT AND CLK=1 THEN IF ENA=1 THEN IF CQI9 THEN CQI=CQI+1; ELSE CQI=0; END IF; END IF; END IF; END PROCESS; PROCESS(CQI) BEGIN IF CQI=9 THEN CARRY_OUT=1; ELSE CARRY_OUT=0; END IF; END PROCESS; CQ=CQI; END behav; 2、锁存器REG32B LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG32B IS PORT(load:IN STD_LOGIC; DIN:IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END R