verilog篮球三十秒可控计时器的代码哦.docVIP

程序 module BTimer(clk,load,stop,qh,ql,alarm); input clk; input load; input stop; output [7:4]qh; output [3:0]ql; output alarm; reg[7:4]qh;//?????????? reg[3:0]ql; reg alarm; wire clk_2; always @ (posedge clk_2 or posedge load) begin if(load) //??load=1,??q=30; begin qh=4d3; ql=0; alarm=0; end else if(stop==0) //?load=0?stop=0.?????? begin if(qh==0ql==0) //?????????qh???ql begin alarm=1; end else if(ql==0) begin qh=qh-1; ql=4d1001; end else begin ql=ql-1; end end else begin //???????????????? end end odd_division div(.clk(clk),.rst(load),.clk_odd(clk_2)); endmodule //????25000??? module odd_division(clk,rst,clk_odd); input clk,rst; output clk_odd; reg clk_odd; reg[15:0] count; parameter N = 25000; always @ (posedge clk) if(rst) begin count = 16d0; clk_odd = 1b0; end else if ( count == N/2-1) begin count = count + 1; end else begin count = 16d0; clk_odd = ~clk_odd; end endmodule 测试程序 module testBT; // Inputs reg clk; reg load; reg stop; // Outputs wire [7:4] qh; wire [3:0] ql; wire alarm; // Instantiate the Unit Under Test (UUT) BTimer uut ( .clk(clk), .load(load), .stop(stop), .qh(qh), .ql(ql), .alarm(alarm) ); initial begin // Initialize Inputs clk 0; load = 1; stop = 0; // Wait 100 ns for global reset to finish #100 load=0; #1250 stop=1; #10 stop=0; forever begin // Initialize Inputs clk = 0; load = 1; stop = 0; // Wait 100 ns for global reset to finish #10 load=1; #1250 stop=1; #10 stop=0; end end always #10 clk=~clk; endmodule