vhdl实现交通灯.docVIP

LED.、数码管交通灯 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity jiaotongdeng is port(clk:in std_logic; rst:in std_logic; en_led:out std_logic_vector(3 downto 0); en_seg:out std_logic_vector(1 downto 0); data_led:out std_logic_vector(2 downto 0); data_seg:out std_logic_vector(7 downto 0) ); end jiaotongdeng; architecture behav of jiaotongdeng is signal saomiao:integer range 0 to 1; signal tim:integer range 0 to 59; signal red_tim:integer range 0 to 59; signal green_tim:integer range 0 to 40; signal tim_ge:integer range 0 to 9; signal tim_shi:integer range 0 to 5; signal cnt_led:integer range 0 to 2:=0; signal yew_tim:integer range 0 to 20; signal tmp:integer range 0 to 2; begin en_led=0000; p1:process(clk) variable cnt:integer range 0 to 7999999; begin if clkevent and clk=1 then if cnt=7999999 then cnt:=0; if cnt_led=0 then if red_tim=0 then red_tim=10; tmp=1; if cnt_led=2 then cnt_led=0; else cnt_led=cnt_led+1; end if; else red_tim=red_tim-1; end if; elsif cnt_led=1 then if yew_tim=0 then yew_tim=20; tmp=2; if cnt_led=2 then cnt_led=0; else cnt_led=cnt_led+1; end if; else yew_tim=yew_tim-1; end if; elsif cnt_led=2 then if green_tim=0 then green_tim=40; tmp=0; if cnt_led=2 then cnt_led=0; else cnt_led=cnt_led+1; end if; else green_tim=green_tim-1; end if; end if; else cnt:=cnt+1; end if; end if; end process; p2:process(clk,rst)- variable cnn1:integer range 0 to 7999; begin if rst=0 then cnn1:=0; elsif clkevent and clk=1 then if cnn1=7999 then cnn1:=0; if saomiao=1 then saomiao=0; else saomiao=saomiao+1; end if; else cnn1:=cnn1+1; end