CMOS超大规模集成电路设计经典教材幻灯片.pptVIP

* * * * * * * * * * * * * * * * * * * * * * * Self-Aligned Process Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact 0: Introduction * N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing 0: Introduction * N-diffusion cont. Historically dopants were diffused Usually ion implantation today But regions are still called diffusion 0: Introduction * N-diffusion cont. Strip off oxide to complete patterning step 0: Introduction * P-Diffusion Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact 0: Introduction * Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed 0: Introduction * Metalization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires 0: Introduction * Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of l = f/2 E.g. l = 0.3 mm in 0.6 mm process 0: Introduction * Simplified Design Rules Conservative rules to get you started 0: Introduction * Inverter Layout Transistor dimensions specified as Width / Length Minimum size is 4l / 2l, sometimes called 1 unit In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long 0: Introduction * Summary MOS transistors are stacks of gate, oxide, silicon Act as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors Now you know everything necessary to start designing schematics and layout for a simple chip! 0: I