大量的verilog源代码.docxVIP

Verilog HDL 程序举例一，基本组合逻辑功能：双向管脚（clocked bidirectional pin）Verilog HDL: Bidirectional PinThis example implements a clocked bidirectional pin in Verilog HDL.The value of OE determines whether bidir is an input, feeding in inp, or a tri-state, driving out the value b.bidir.vmodulebidirec (oe, clk, inp, outp, bidir);// Port Declarationinputoe;inputclk;input [7:0] inp;output [7:0] outp;inout [7:0] bidir;reg [7:0] a;reg [7:0] b;assignbidir = oe ? a : 8bZ ;assignoutp = b;// Always Constructalways @ (posedgeclk)begin b = bidir; a = inp;endendmodule多路选择器（MUX）////-----------------------------------------------------------------------------------// DESCRIPTION : Multiplexer// Code style: used case statement// Width of output terminal: 8// Number of terminals: 4// Output enable active: HIGH// Output value of all bits when enable not active: 0//-----------------------------------------------------------------------------------module mux(EN ,IN0 ,IN1 ,IN2 ,IN3 ,SEL ,OUT );input EN ;input [7:0] IN0 ,IN1 ,IN2 ,IN3 ;input [1:0] SEL ;output [7:0] OUT ;reg [7:0] OUT ;always @(SEL or EN or IN0 or IN1 or IN2 or IN3 )beginif (EN == 0) OUT = {8{1b0}};elsecase (SEL )0 : OUT = IN0 ;1 : OUT = IN1 ;2 : OUT = IN2 ;3 : OUT = IN3 ;default : OUT = {8{1b0}};endcaseendendmodule二进制到BCD码转换//// //-----------------------------------------------------------------------------------// DESCRIPTION : Bin to Bcd converter// Input (data_in) width : 4// Output (data_out) width : 8// Enable (EN) active : high//-----------------------------------------------------------------------------------module bin2bcd (data_in ,EN ,data_out );input [3:0] data_in ;input EN ;output [7:0] data_out ;reg [7:0] data_out ;always @(data_in or EN )begindata_out = {8{1b0}};if (EN == 1)begincase (data_in [3:1]) 3b000 :data_out [7:1] = 7b0000000;3b001