[信息与通信]论文_IC_验证.docVIP

FF-DX半定制/全定制混合设计流程中 功能与时序验证 摘 要 随着集成电路的规模和复杂度不断增大，验证的作用越来越重要。要在较短的时间内保证芯片最终能正常工作，需要将各种验证相结合，全面充分地验证整个系统。为了在提升芯片性能的同时，缩短设计周期，降低开发成本，采用了半定制/全定制混合设计的方法，对RTL级代码进行优化改进，采用全定制设计实现。混合设计复杂性，给验证工作带来挑战。本文针对半定制/全定制混合设计的特点，主题词：半定制/全定制混合设计，验证，时序，静态时序分析ABSTRACT The complexity and size of the modern VLSI has been increasing dramatically, which present a significant challenge for verification. In order to ensure proper function of the design, various methods need to be used to verify the entire system sufficiently. FF-DX, a high-performance fix-point DSP our group designed, has adopted several design methods to enhance performance, as well as cut down design cycle and lower the cost. The most featured one is what we called blended methodology which mixes semi-custom and full-custom design methods together. Nevertheless, this methodology has led to a huge challenge to verification because of the complexity it brings in. In this dissertation, based on the characteristics of the blended methodology, we propose a flow for functional and timing verification, with the novel idea of combining full-custom and semi-custom verification methods. We verify the branch control function unit in three aspects, simulation verification, equivalence verification, together with functional verification in the full-custom designs. A blended methodology is introduced to generate the testbench for functional verification, which combines both manual and pseudo-random methods, and after evaluation, the code coverage rate is 98%. We also adopt a new methodology of combining the NC-Verilog simulator with functional model extractor TranSpirit for full-custom block ,and it speed up verification efficiency. Besides, we studied equivalence verification, a formal verification methodology which is used for RTL-RTL and RTL-gate design. To guarantee the functional equivalence between RTL design and full-custom design further, we design a testbench which can verify the two designs at the same time a